1. Field of the Invention
The present invention relates to a semiconductor memory device for read-only operations which has data written into it at the time of its manufacture and which subsequent to manufacture serves only for read-out of this data.
2. Description of the Prior Art
A read-only memory (referred to below ans a ROM) that serves only for read-out of data is commonly called a mask-program ROM, since data is written into it during the wafer processing stage. There are three types of process in general use for writing in ROM data, (a) a contact process, (b) the SDG process and (c) a process making use of differences in transistor threshold voltages. With process (a), whether "1" level or "0" level data is written in depends on whether or not a data line and the drain of a memory cell transistor is connected by a contact. With process (b), write-in of "1" or "0" data depends on whether a gate oxide film or a field oxide film is formed in the gate region of a memory cell transistor. With process (c), the data written in depends on whether a memory cell transistor's threshold voltage is made high or is left low.
ROMs for which the contact process (a) is employed have the drawback that they have a larger memory cell area than ROMs for which process (b) or (c) is employed, since each individual memory cell needs an individual contact.
FIG. 1 is a circuit diagram of a conventional ROM in which data write-in is effected by process (b) or (c) and FIG. 2 is a plane view of the pattern of two memory cells of this ROM. In these drawings, lines 41 are memory cell gate lines, lines 42 are ROM data lines, lines 43 are ground connection lines, transistors 44 are MOS transistors which constitute memory cells and whose threshold voltages are selectively made high depending on the data written into them and contacts 45 are connected data lines 42 and the drains of memory cell MOS transistors 44. The portion enclosed by the two-dot chain line of FIG. 2 is one memory cell region. Memory cell gate lines 41 are, for example, constituted by polycrystalline silicon whose resistance has been made low by introduction of an impurity. Data lines 42 are constituted by a metal such as aluminium, etc.
With ROMs in which write-in of data is effected by the SDG process (b) or by process (c) employing differences in transistor threshold voltages, the memory cell size can be made smaller than in a ROM for which the contact process (a) is employed, since there only needs to be one contact for every two memory cells. In ROMs for which thes processes are employed, memory cell size going vertically as seen in the drawing is determined by the size of the contact and the interval, indicated as dimension "1" in FIG. 2, between contact 45 and gate line 41. If one tries reducing the size of contact 45 in order to reduce the area occupied by the cell, the result is that the resistance of the contact portions becomes a resistance of a magnitude that cannot be ignored, which means that there are limits to how small contact 45 can be made, and hence limits to reduction of the memory cell size.
Because of this, there has been furthr development in the past to give a ROM which permits reduction of the area occupied by memory cells and hence an increase in capacity. In this ROM, the drain region of a memory cell transistor formed in a silicon semiconductor substrate is connected to a wire which is constituted by silicon, the same material as the drain region, and which extends to above the gate electrode structure. This allows the contact between this wire and a metal wire constituting a data line to be larger. FIG. 3 shows a plane view of the pattern of two memory cells in a ROM such as this. FIG. 4 shows a section along the line a--a' of FIG. 3. In FIGS. 3 and 4, substrate 51 is a P type silicon semiconductor substrate, region 52 is an N.sup.+ drain region, region 53 is an N.sup.+ source region, layers 54 are gate electrodes constituted by a first polycrystalline silicon layer whose resistance has been made low by the introduction of an impurity, films 55 are insulating films that covers gate electrodes 54 and substrate 51, layer 56 is a wire constituting by a second polycrystalline silicon layer, hole 57 is a contact hole between drain region 52 and wire 56 and hole 58 is a contact hole between wire 56 and a data line 59 of aluminium. The portion enclosed by the one-dot chain line is one memory cell 60 and 61 is a MOS transistor.
In a ROM with this structure, transistor drain region 52 formed in semiconductor substrate 51 and layer 56 constituted by silicon are connected directly via contact hole 57, in a so-called buried method and since there is contact between silicon and silicon, the contact resistance is small and the area of contact hole 57 can be made small. The area occupied by memory cells in this ROM can be reduced to around 85% of the area of memory cells in an SDG process or ion implantation process memory in which the memory cell drain regions are connected to aluminium data lines. Also, since the area of contact hole 58 between aluminium data line 59 and layer 56 constituted by a second layer of polycrystalline silicon can be made larger, the contact resistance in this portion is smaller and so there is no deterioration of transistor characteristics because of contact resistance.
However, the ROM of FIGS. 3 and 4 still has the problem that if the memory capacity is increased still further, the dimensional allowances to allow for misalignment at sections "d" in FIG. 4 in formation of contact hole 57 comes to represent a large proportion of the memory cell dimension in one direction. There are limits to how far the precision of mask alignment can be improved and one cannot hope for any great increase in density unless this problem is solved.